Post-Silicon Validation

Course Hours: 30 hrs

Course Time: 10/30/2017 - 12/7/2017

Course Arrangement:  Monday & Thursday 6pm to 9pm for 5 weeks

Fee: $850

Prerequisite: understainiding basic engineering concepts

Category: VLSI

Job Opportunities: Companies are spending more resources on Post-Silicon Validation efforts to make sure silicon quality improves, there are fewer bugs in silicon, and addressing customer needs by bringing product to market faster. Every Hardware company needs post-silicon validation engineering to deliver successful products to market by catching bugs early.

Course description:

Post-silicon validation remains an integral and crucial phase of today’s ASIC design and manufacturing process. The growing importance of post-silicon validation in ensuring functional correctness of complex designs increases the need for synergy between the pre-silicon verification and post-silicon validation. This course is designed to give students an opportunity to learn about ASIC high-speed system level design and validation methodology and Post-Silicon Validation challenges with ever-increasing complexity of design and shorter time to market cycle.

 

This course provides a great opportunity for students to learn about basic concepts of ASIC validation methodology, high-speed circuit design fundamentals, system design considerations, validation strategies for complex ASIC’s designed for today’s market needs. Students will be engaged in a real-time project related to a networking ASIC, and they will participate in hands-on exercises throughout the course.

Course Outline:

- Course Overview and Objectives, Fundamentals of ASIC Post-Silicon Validation. High-Speed system-Level Platform Design for Post-Silicon Validation. ASIC Validation Challenges and Opportunities, ASIC Validation Flow from Manufacturing to Mass Production.

- Schematics capture using OrCAD, schematics connection rules, symbol creation, off page connection, DRC (design rule check) checking. Transmission line theory and termination scheme to improve signal integrity.

- PCB design, PCB stack up, Selecting pcb trace impedance calculation, system level design analysis, differential pair routing, cross talk. EMI Issues – Frequency, Amplitude, Time, Impedance Dimensions. Why parts placement, proper terminations and grounding are so important for EMI.

- Verification of hardware platform for clocks, reset and voltages without the silicon on the board (with sockets for placing the silicon). Verification of the clock and reset generation after placing the ASIC on the board. Follow the Interface bring-up plan to bring up various functional blocks in the ASIC. Verify power sequence and should be followed as defined by the silicon specification.

- Defining functional test plan based on specification. ASIC functional validation over normal operating condition (NVNT), functional validation over (LVNT, LVLT, LVHT, HVNT, HVLT, HVHT). Automating functional tests, Detecting bugs by running functional test programs until the DUT under test malfunctions. Localizing the problem to a small region isolated region in ASIC. Debugging and identifying the root cause of the functional bugs. Fixing functional bugs or bypassing the bug. Identifying corner cases and running test program to catch critical silicon bugs.

- High-speed interface Electrical characterization (like USB, Serdes, SATA, PCI express etc.). Digital I/O timing characterization (such as XMII Interfaces). Electrical compliance test (Jitter, Amplitude, Eye diagram etc.), ASIC characterization over PVT. Protocol compliance test (USB, Ethernet, DDR etc.), Clock characterization. Rise & fall time, slew rate, set up and hold time characterization.

- Automated test pattern generation and automated result checking. Continuous power cycle test, continuous reset test, continuous data path test, regression test over worst condition (worst voltage, temperature and process corner), Long term BER (bit error rate) test, performance test, asynchronous vs synchronous test, ATE – Automated Test Equipment and its components Load boards, Probe cards, Handlers, Probers (Why ATE? Testing large no. of devices means more profitability). AC Parameters Test AC Timing Tests - Setup Time, Hold Time, Propagation Delay, and Timing Calibration. Memory BIST test (BIST: is a design technique in which parts of a circuit are used to test the circuit itself) and scan test.

- System level hardware board schematics design using post-silicon design flow and project submission.

Learning Outcome:

  1. Students will be able to apply electrical engineering knowledge to system level hardware design for post-silicon validation. Graduates will be able to develop deeper understanding of post-silicon validation methodology, planning, and execution strategy in today's complex VLSI circuits.
  2. Graduates will be able to use modern hardware design tools for simulations, validations, and analysis.
  3. Students will be able to perform high-speed board design using schematics capture tools, hardware bring up/debug, high-speed interface electrical and timing characterization.
    4.   Students will be able to apply EE core knowledge to debug logical and electrical bugs in silicon, root-cause analysis and issue closure.

Instructor:

Experiences in the Field