Concentrating Electives in
VLSI Engineering Course

CONCENTRATING ELECTIVES IN VLSI ENGINERRING COURSES (VE 510 – VE 520)

 

Course Prefix & No.: VE 510
Units: 3
Course Title: Soc Design
Prerequisite: C programing Language
Course Description
The purpose of this course is to introduce the graduate students to System-on-Chip design and development process, including architecture design, processor & memory, IP integration, and platform development.

Topics covered in this course are: Hardware Description Language (HDL), SoC architecture design and planning, Processors, Memory design, on chip interconnection network, IP selection, verification, and integration, SoC platform development.

Learning outcomes of this course are students will be proficient in fundamental concepts of SoC design and implementation, including SoC architecture, basic building blocks for SoC, design language & tools, IP, and platform development consideration.

Course Prefix & No.: VE 511
Units: 3
Course Title: Digital Logic Design Using Verilog
Prerequisite: VE 503
Course Description
The purpose of this course is to provide the graduate students with the fundamental aspects of logic design systems, verilog constructs and hardware modeling techniques.

Topics covered in this course are: digital design specification, sub-systems logic design, design integration, design validation, and verilog model design including language elements, data types, structural, dataflow & behavioral modeling, and common constructs & coding consideration.
Learning outcomes of this course are to understand the logic design concepts such as speed, area, power, cost, and testability. The students are required to implement a complete digital system project from specification to validation. It also requires the students to implement Verilog modeling of digital logic.

Course Prefix & No.: VE 512
Units: 3
Course Title: Logic Synthesis
Prerequisite: VE 503
Course Description
The purpose of this course is to provide the graduate students with the fundamentals of gate-level synthesis of VLSI circuits. This class also presents the logic synthesis techniques for the automation of VLSI design flow.

Topics covered in this course are: logic synthesis concepts and methods, design partitioning, technology library, design constraints setup, gate-level optimization, timing analysis, and library management.

Learning outcomes of this course are to understand the concepts and role played of logic synthesis in VLSI design flow and use the Synopsys tools to synthesizing high-level hardware description languages such as Verilog or VHDL to implement the gate-level netlist.

Course Prefix & No.: VE 513
Units: 3
Course Title: Physical Design
Prerequisite: VE 503
Course Description (Required course for IC Physical Design certification)
The purpose of this course is to provide the graduate students with the fundamentals of Place and Route (P&R) knowledge and skills and also analyzed its role played in VLSI design flow.

Topics covered in this course are: Process Technology file generation, Macro LEFs creation, floor planning, placement, power planning, DEF generation, timing optimization, clock tree synthesis, global & detail routing, RC extraction, static timing analysis, IR drops, signal integrity, and ECO flow.

Learning outcomes of this course are utilizing the basic concept of P&R flow to implement the in-class industry project exercises using Cadence SoC Encounter tool. The students can also learn how to automate and analyze P&R flow process by using scripts.

Course Prefix & No.: VE 514
Units: 3
Course Title: Fundamental IC Layout Design
Prerequisite: Graduate Standing
Course Description (Required course for IC Physical Design certification)
The purpose of this course is to provide the graduate students with the fundamental aspects of CMOS IC layout from concepts, methodologies, tools, and design flow points of view.

Topics covered in this course are: Basic transistor concept, CMOS theories, CMOS process, CMOS logic gates, layout design rules, logic reduction using K-map, DRC/LVS verification, resistor & capacitor theory, latch-up prevention concept, substrate/well taps, ESD theory, and bipolar & analog layout theories.

Learning outcomes of this course are to understand the CMOS IC layout concept and layout drawing skills. The students can learn how to implement the full-custom and standard cells design using Cadence Virtuoso Layout tool and also learn how to resolve the layout design issues.

Course Prefix & No.: VE 515
Units: 3
Course Title: Advanced IC Layout Design
Prerequisite: VE 514
Course Description (Required course for IC Physical Design certification)
The purpose of this course is to provide the graduate students with more advanced CMOS IC layout knowledge and skills. The intensive hands-on labs also train students independently implement the chip-level industry layout project.

Topics covered in this course are: memory theory, Pcell design, balanced layout design, layout design using VXL, DRC/LVS debugging, spice netlist creation, pad cell and ESD layout structure, bipolar & analog layout design, chip floor planning, power grid consideration, and vi editor.

Learning outcomes of this course are to gain more advanced layout design knowledge and tool skills. The students are required to implement a chip-level SRAM project design using Cadence Opus tool and also have the capability to debug the DRC/LVS issues.

Course Prefix & No.: VE 516
Units: 3
Course Title: Physical Verification for Manufacturing
Prerequisite: VE 514
Course Description
The purpose of this course is to provide the graduate students with the fundamentals of physical verification and know how’s to design layout for manufacturing with high yield.

Topics covered in this course are: Introduction to semiconductor manufacturing, process technology rule creation, design rule check, antenna check, electrical rule check, layout versus schematic, parasitic resistance and capacitance extraction, post-layout chip integration, design for manufacturing checks.

Learning outcomes of this course are utilizing the basic concept of IC physical verification to practice the advanced physical design rule checks and implement industry-standard IC layout verification project using Calibre tools. The students also learn how to automate IC integration flow and ensure DFM success.

Course Prefix & No.: VE 517
Units: 3
Course Title: Design and Implementation
Prerequisite: VE 503
Course Description
The purpose of this course is to enable the graduate students to design and implement the custom computing systems with field programmable gate arrays (FPGAs).

Topics covered in this course are: computing methods comparison, VHDL introduction, FPGA architectures fundamentals, FPGA placement and routing, FPGA configuration, reconfigurable computing architectures, reconfigurable computing applications, high-level compilation, and hardware & software partitioning.

Learning outcomes of this course are to have students to gain the different technologies to implement the digital computing systems, to know various FPGA architectures, and to learn the automated design flow to support designs with FPGAs. This course also provides the design tools to support the FPGA-based system designs and their applications in reconfigurable computing.

Course Prefix & No.: VE 518
Units: 3
Course Title: Low Power Systems Design
Prerequisite: Undergraduate Microprocessor design
Course Description
The purpose of this course is to provide the graduate students the practical aspects of engineering high-performance computer systems where power consumption is a major consideration at every stage of the design.

Topics covered in this course are: The ARM 32-bit RISC microprocessor, a world-leading processor for power-sensitive applications, and covers many aspects of designing power-efficient systems around ARM cores.

Learning outcomes of this course are to understand the principles of low-power RISC processor design, and to apply a systematic methodology to memory hierarchy design.

Course Prefix & No.: VE 519
Units: 3
Course Title: Wireless Design
Prerequisite: VE 502, VE 503
Course Description
The purpose of this course is to provide the graduate students a solid introduction to the design of wireless communication systems, highlighting common themes and basis techniques.

Topics covered in this course are: A typical wireless project involves multiple components to be integrated such as, RF/microwave circuitry, antenna, electronic circuits, microprocessors circuit/programming, digital signal processing (DSP) and communication system analysis and design.

Learning outcomes of this course are to work in a team environment design and built a wireless communication system.

Course Prefix & No.: VE 520
Units: 3
Course Title: Nano Structures and Quantum Devices
Prerequisite: College Physics
Course Description
The purpose of the course is to provide students with theoretical background of nanostructures based on quantum mechanical origin. The quantum mechanical concepts applied to model and analyze nanoscale devices are also presented.

Topics covered in this course are: Nano World and Quantum Mechanics, Wave Functions in Nanoscale, Layered Nanostructures and Tunneling, Quantization in Nanostructures, Density of States in Quantum Box, Quantum Wells, Quantum Wires and Quantum Rings, Electron Transport in Nanostructures, Coulomb Blockade and Single Electron Tunneling, Nanostructure Devices, Mesoscopic Superlattices, Spintronics and Quantum Optical Devices.

Learning outcomes of this course are: students are able to learn theoretical methods of analyzing electronic and optical properties of low-dimensional heterostructures. Also students are able to model microelectronic devices and ultimately toward nano electronic and nano optical devices.